1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a transistor without defining the sidewall surfaces of the gate conductor prior to implantation of dopant into the transistor junctions.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide arranged above a semiconductor substrate. The polysilicon material and the gate oxide are patterned to form a gate conductor with source/drain regions within the substrate adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
FIGS. 1-4 illustrate the fabrication of a conventional transistor. A semiconductor substrate 10 is provided upon which a gate oxide 12 has been thermally grown. A polysilicon layer 14 has been deposited across gate oxide 12 using chemical-vapor deposition ("CVD"). Portions of polysilicon layer 14 and gate oxide 12 are removed to define a gate conductor 18 dielectrically spaced above substrate 10, as shown in FIG. 2. A lightly doped drain ("LDD") implant self-aligned to the opposed sidewall surfaces of gate conductor 18 is then forwarded into substrate 10 to form LDD areas 20 on opposite sides of the gate conductor. Thereafter, a dielectric material 22, e.g., silicon dioxide ("oxide") is deposited across gate conductor 18 and substrate 10. The dielectric material 22 is then removed from horizontally oriented surfaces while being retained upon the sidewall surfaces of gate conductor 18 using an anisotropic etch technique, thereby forming sidewall spacers 24. A source/drain ("S/D") implant self-aligned to the exposed lateral edges of sidewall spacers 24 is forwarded into substrate 10 to form source/drain regions 26. The S/D implant species are implanted at a higher dose and higher energy than those implanted into LDD areas 20. As a result, the peak concentration of dopant species within source/drain regions 26 is greater than that of the more shallow LDD areas 20.
The combination of LDD areas 20 and source/drain regions 26 form source-side and drain-side graded junctions on opposite sides of the resulting transistor. The LDD areas 20 can absorb some of the potential at the interface between the channel and the junctions. Unfortunately, during ion implantation of dopant into source/drain regions 26 and LDD areas 20, ions may impinge the lateral edges of gate conductor 18 and sidewall spacers 24. The ions lose their energy in a series of nuclear and electronic collisions and come to rest in close proximity to lateral edges of gate conductor 18 and sidewall spacers 24. As a result, more dopant species accumulate near the lateral edges of gate conductor 18 than in other portions of the gate conductor. During subsequent anneal steps, these dopant species may deleteriously migrate into the underlying channel region, and thereby increase potential gradients in the device. The maximum electric field, Em, occurring near the drain-side junction during saturated operation of the transistor may consequently be increased, despite the presence of LDD areas 20. The existence of an electric field at the drain of an operating transistor primarily causes electrons in the channel to gain kinetic energy and become "hot", leading to a phenomenon known as hot-carrier effect ("HCE"). As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain-side junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge can accumulate with time, resulting in a positive threshold shift in an NMOS transistor, or a negative threshold shift in a PMOS transistor. Since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in NMOS transistors than PMOS transistors.
The nuclear collisions of energetic ions with atoms within polysilicon gate conductor 18 and oxide-based sidewall spacers 24 may cause damage at the lateral edges of these structure. Various defects may form near the edges of gate conductor 18 and sidewall spacers 24. The energetic ions may dislodge atoms from their original positions, resulting in the formation of vacancies and dangling bonds within gate conductor 18 and sidewall spacers 24. Unfortunately, such vacancies and dangling bonds may serve as traps to foreign atoms, e.g., hydrogen, and hot electrons. Hydrogen atoms thus may form weak Si-H bonds at the gate conductor/gate dielectric interface. These bonds can be easily broken by injected hot electrons. The presence of foreign atoms within gate conductor 18 and sidewall spacers 24 can alter the properties of these structures in a detrimental manner. For instance, the presence of foreign atoms within gate conductor 18 may cause the resistivity of the gate conductor edge to increase, and thereby lead to a shift in the threshold voltage, V.sub.T, from its desired value.
It would therefore be desirable to develop a transistor fabrication technique in which problems associated with ion bombardment of the lateral edges of the transistor gate conductor and sidewall spacers are alleviated. More specifically, a process is needed in which ions are prevented from striking the lateral edges of the gate conductor and the sidewall spacers during implantation of dopant into transistor junctions. As such, dopant species would no longer be allowed to accumulate more so near the edges of the gate conductor than other regions of the gate conductor. Thus, less dopant species would be available in the gate conductor to migrate to the lateral junction at the drain adjacent the channel and thereby result in an undesirable increase in Em. Moreover, damage incurred by collisions between energetic ions and atoms within the gate conductor and sidewall spacers would be prevented. Accordingly, foreign atoms and hot electrons would be less likely to become trapped in the gate conductor and sidewall spacers. Problems associated with HCE would be less probable.